~8 ( ^google,veyron-mickey-rev8google,veyron-mickey-rev7google,veyron-mickey-rev6google,veyron-mickey-rev5google,veyron-mickey-rev4google,veyron-mickey-rev3google,veyron-mickey-rev2google,veyron-mickey-rev1google,veyron-mickey-rev0google,veyron-mickeygoogle,veyronrockchip,rk3288&7Google Mickeyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12P'@5Hcpu@502cpuarm,cortex-a12P'@5Hcpu@503cpuarm,cortex-a12P'@5Hcpu-opp-tableoperating-points-v2aHopp-126000000ls opp-216000000l s opp-408000000lQs opp-600000000l#Fs opp-696000000l)|s~opp-816000000l0,sB@opp-1008000000l<sopp-1200000000lGsopp-1416000000lTfrsOopp-1512000000lZJsopp-1608000000l_"s opp-1704000000lespopp-1800000000lkIs\amba simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkHdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkHWreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample)  @4reset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 5Eswbiuciuciu-driveciu-sample) ! @4resetokay@J[h~ default dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample) "@4reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample) #@4resetokay@-~default saradc@ff100000rockchip,saradc $85I[saradcapb_pclkW 4saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclkJ  Otxrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclkJ Otxrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclkJOtxrx .default !"#okayY flash@0jedec,spi-norli2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$okay~2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault& disabled~2,i2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault'okay~,Hmserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkdefault ()*okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkdefault+okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault,okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkdefault- disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkdefault. disabledthermal-zonesreserve_thermal%/cpu_thermald%/tripscpu_crit5_A criticalcpu_alert_almost_warm5Apassivecpu_alert_warm5ApassiveH0cpu_alert_almost_hot58ApassiveH1cpu_alert_hot5@PApassiveH2cpu_alert_hotter5H ApassiveH3cpu_alert_very_hot5LApassiveH4cooling-mapscpu_warm_limit_cpuL0 Qcpu_almost_hot_limit_cpuL1 Qcpu_hot_limit_cpuL2 Qcpu_hotter_limit_cpuL3 Qcpu_very_hot_limit_cpuL4 Qgpu_thermald%/tripsgpu_alert05pApassiveH5gpu_crit5_A criticalcooling-mapsmap0L5 Qtsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 4tsadc-apbinitdefaultsleep6`7j6tsokayH/ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq885fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 4stmmaceth disabledusb@ff500000 generic-ehciP 5usbhost9usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost: usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otghost/>@@ ; usb2-phyokayzM;usb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault<okay~2dpmic@1brockchip,rk808xin32kwifibt_32kin&=default >?@dAB BH|regulatorsDCDC_REG1vdd_arm"4 qL dqH regulator-state-memyDCDC_REG2vdd_gpu"4 5LdqHqregulator-state-memB@DCDC_REG3 vcc135_ddr"regulator-state-memDCDC_REG4vcc_18"4w@Lw@Hregulator-state-memw@LDO_REG3vdd_10"4B@LB@regulator-state-memB@LDO_REG7 vdd10_lcd"4B@LB@SWITCH_REG1 vcc33_lcd"HVregulator-state-memyLDO_REG8"4w@Lw@ vcc18_lcdi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultC disabled~2 pwm@ff680000rockchip,rk3288-pwmhdefaultD5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultE5^pwmokaypwm@ff680020rockchip,rk3288-pwmh defaultF5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultG5^pwm disabledbus_intmem@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controllerhM HZpd_vio@9 5chgfdehilkj$HIJKLMNOPpd_hevc@11 5opQRpd_video@12 5Spd_gpu@13 5TUreboot-modesyscon-reboot-mode RBRB,RB dvs-1 uH?dvs-2uH@rebootap-warm-reset-h sHyrecovery-switchrec-mode-l ttpmtpm-int-hswrite-protectfw-wp-apsmemorymemorygpio-keys gpio-keysdefaultxpower Power = t dgpio-restart gpio-restart = defaulty &emmc-pwrseqmmc-pwrseq-emmczdefault /{ Hsdio-pwrseqmmc-pwrseq-simple5| ext_clockdefault}~ /H vcc-5vregulator-fixedvcc_5v"4LK@LLK@ ;Hvcc33-sysregulator-fixed vcc33_sys"42ZL2ZHvcc50-hdmiregulator-fixed vcc50_hdmi" ; F YB defaultvcc33_ioregulator-fixed vcc33_io" ;HA #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleoperating-pointsopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wp#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvddio-supplydvs-gpiosvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cells#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpio