A8( mKgoogle,veyron-brain-rev0google,veyron-braingoogle,veyronrockchip,rk3288& 7Google Brainaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12P'@5Hcpu@502cpuarm,cortex-a12P'@5Hcpu@503cpuarm,cortex-a12P'@5Hcpu-opp-tableoperating-points-v2aHopp-126000000ls opp-216000000l s opp-408000000lQs opp-600000000l#Fs opp-696000000l)|s~opp-816000000l0,sB@opp-1008000000l<sopp-1200000000lGsopp-1416000000lTfrsOopp-1512000000lZJsopp-1608000000l_"s opp-1704000000lespopp-1800000000lkIs\amba simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkHdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkHTreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample)  @4reset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 5Eswbiuciuciu-driveciu-sample) ! @4resetokay@J[h~ default dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample) "@4reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample) #@4resetokay@-8~default saradc@ff100000rockchip,saradc $G5I[saradcapb_pclkW 4saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclkY  ^txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclkY ^txrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclkY^txrx .default !"#okayh flash@0jedec,spi-nor{i2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault&okay2,i2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault'okay,Hjserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkdefault ()*okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkdefault+okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault,okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkdefault- disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkdefault. disabledthermal-zonesreserve_thermal&4/cpu_thermald&4/tripscpu_alert0DpPpassiveH0cpu_alert1D$PpassiveH1cpu_critD_P criticalcooling-mapsmap0[0 `map1[1 `gpu_thermald&4/tripsgpu_alert0DpPpassiveH2gpu_critD_P criticalcooling-mapsmap0[2 `tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 4tsadc-apbinitdefaultsleep3o4y3sokayH/ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq585fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 4stmmaceth disabledusb@ff500000 generic-ehciP 5usbhost6usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otg$host7 usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg$host,>M@@ 8 usb2-phyokayz\8usb@ff5c0000 generic-ehci\ 5usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault9okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&:default ;<=s>? ?HyregulatorsDCDC_REG1vdd_arm1C q[ sqH regulator-state-memDCDC_REG2vdd_gpu1C 5[sqHnregulator-state-memB@DCDC_REG3 vcc135_ddr1regulator-state-memDCDC_REG4vcc_181Cw@[w@Hregulator-state-memw@LDO_REG3vdd_101CB@[B@regulator-state-memB@LDO_REG7 vdd10_lcd1CB@[B@regulator-state-memSWITCH_REG1 vcc33_lcd1HSregulator-state-memSWITCH_REG21 vcc18_hdmii2c@ff660000rockchip,rk3288-i2cf =i2c5Ndefault@okay2 pwm@ff680000rockchip,rk3288-pwmhdefaultA5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhdefaultB5^pwmokaypwm@ff680020rockchip,rk3288-pwmh defaultC5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultD5^pwm disabledbus_intmem@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controllerh\ HWpd_vio@9 5chgfdehilkj$EFGHIJKLMpd_hevc@11 5opNOpd_video@12 5Ppd_gpu@13 5QRreboot-modesyscon-reboot-mode!RB-RB;RB KRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5WHjk$#gׄeрxhрxhHsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwH5edp-phyrockchip,rk3288-dp-phy5h24md disabledHgio-domains"rockchip,rk3288-io-voltage-domainokayo>y>>Susbphyrockchip,rk3288-usb-phyokayusb-phy@320d 5]phyclkH8usb-phy@334d45^phyclkH6usb-phy@348dH5_phyclkH7watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk5TYT^tx 6defaultU5 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5YTT^txrxi2s_hclki2s_clk5RdefaultV disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk 4crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk6W ilm 4coreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop6W def 4axiahbdclkDXokayportH endpoint@0KYHkendpoint@1KZHhendpoint@2K[Hbendpoint@3K\Heiommu@ff930300rockchip,iommu  vopb_mmu5 aclkiface6W okayHXvop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vop6W  4axiahbdclkD] disabledportH endpoint@0K^Hlendpoint@1K_Hiendpoint@2K`Hcendpoint@3KaHfiommu@ff940300rockchip,iommu  vopl_mmu5 aclkiface6W  disabledH]mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk6W 5 disabledportsportendpoint@0KbH[endpoint@1KcH`lvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcd6W 5 disabledportsport@0endpoint@0KeH\endpoint@1KfHadp@ff970000rockchip,rk3288-dp@ b5icdppclkgdpo4dp5 disabledportsport@0endpoint@0KhHZendpoint@1KiH_hdmi@ff980000rockchip,rk3288-dw-hdmi5 g5hmniahbisfrcec6W okay[jportsportendpoint@0KkHYendpoint@1KlH^iommu@ff9a0800rockchip,iommu vpu_mmu5 aclkiface disablediommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5m6W okaygngpu-opp-tableoperating-points-v2Hmopp@100000000ls~opp@200000000l s~opp@300000000lsB@opp@400000000lׄsopp@500000000lesOopp@600000000l#Fsqos@ffaa0000syscon HQqos@ffaa0080syscon HRqos@ffad0000syscon HFqos@ffad0100syscon HGqos@ffad0180syscon HHqos@ffad0400syscon HIqos@ffad0480syscon HJqos@ffad0500syscon HEqos@ffad0800syscon HKqos@ffad0880syscon HLqos@ffad0900syscon HMqos@ffae0000syscon HPqos@ffaf0000syscon HNqos@ffaf0080syscon HOinterrupt-controller@ffc01000 arm,gic-400s@ @ `   Hefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrl5defaultsleepooogpio0@ff750000rockchip,gpio-banku Q5@sH:gpio1@ff780000rockchip,gpio-bankx R5Asgpio2@ff790000rockchip,gpio-banky S5BsHxgpio3@ff7a0000rockchip,gpio-bankz T5Csgpio4@ff7b0000rockchip,gpio-bank{ U5DsH|gpio5@ff7c0000rockchip,gpio-bank| V5Esgpio6@ff7d0000rockchip,gpio-bank} W5Fsgpio7@ff7e0000rockchip,gpio-bank~ X5GsH?gpio8@ff7f0000rockchip,gpio-bank Y5Hshdmihdmi-cec-c0phdmi-cec-c7phdmi-ddc ppvcc50-hdmi-enpH~pcfg-pull-upHqpcfg-pull-downHrpcfg-pull-noneHppcfg-pull-none-12ma Htsleepglobal-pwroffpHoddrio-pwroffpddr0-retentionqddr1-retentionqedpedp-hpd ri2c0i2c0-xfer ppH9i2c1i2c1-xfer ppH$i2c2i2c2-xfer  p pH@i2c3i2c3-xfer ppH%i2c4i2c4-xfer ppH&i2c5i2c5-xfer ppH'i2s0i2s0-bus`ppppppHVlcdclcdc-ctl@ppppHdsdmmcsdmmc-clkpsdmmc-cmdqsdmmc-cdqsdmmc-bus1qsdmmc-bus4@qqqqsdio0sdio0-bus1qsdio0-bus4@ssssHsdio0-cmdsHsdio0-clksHsdio0-cdqsdio0-wpqsdio0-pwrqsdio0-bkpwrqsdio0-intqwifienable-hpH{bt-enable-lpHzsdio1sdio1-bus1qsdio1-bus4@qqqqsdio1-cdqsdio1-wpqsdio1-bkpwrqsdio1-intqsdio1-cmdqsdio1-clkpsdio1-pwr qemmcemmc-clksHemmc-cmdsHemmc-pwr qemmc-bus1qemmc-bus4@qqqqemmc-bus8ssssssssHemmc-reset pHwspi0spi0-clk qHspi0-cs0 qHspi0-txqHspi0-rxqHspi0-cs1qspi1spi1-clk qHspi1-cs0 qHspi1-rxqHspi1-txqHspi2spi2-cs1qspi2-clkqH spi2-cs0qH#spi2-rxqH"spi2-tx qH!uart0uart0-xfer qpH(uart0-ctsqH)uart0-rtspH*uart1uart1-xfer q pH+uart1-cts quart1-rts puart2uart2-xfer qpH,uart3uart3-xfer qpH-uart3-cts quart3-rts puart4uart4-xfer qpH.uart4-cts quart4-rts ptsadcotp-gpio pH3otp-out pH4pwm0pwm0-pinpHApwm1pwm1-pinpHBpwm2pwm2-pinpHCpwm3pwm3-pinpHDgmacrgmii-pinsppppttttppp ttpprmii-pinsppppppppppspdifspdif-tx pHUpcfg-pull-none-drv-8maHspcfg-pull-up-drv-8mapcfg-output-highpcfg-output-low buttonspwr-key-lqHupmicpmic-int-lqH;dvs-1 rH<dvs-2rH=rebootap-warm-reset-h pHvrecovery-switchrec-mode-l qtpmtpm-int-hpwrite-protectfw-wp-appusb-hostusb2-pwr-en pHmemorymemorygpio-keys gpio-keysdefaultupower Power : t #dgpio-restart gpio-restart : defaultv 5emmc-pwrseqmmc-pwrseq-emmcwdefault >x Hsdio-pwrseqmmc-pwrseq-simple5y ext_clockdefaultz{ >|H vcc-5vregulator-fixedvcc_5v1CLK@[LK@H}vcc33-sysregulator-fixed vcc33_sys1C2Z[2Z J}Hvcc50-hdmiregulator-fixed vcc50_hdmi1 J} U h?default~vcc33_ioregulator-fixed vcc33_io1 JH>vcc5-host2-regulatorregulator-fixed U h: default vcc5_host21 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleoperating-pointsopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cells#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpio