8l(4'rockchip,rk3288-fennecrockchip,rk3288&7Rockchip RK3288 Fennec Boardaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5< Hcpu@501cpuarm,cortex-a12P'@5Hcpu@502cpuarm,cortex-a12P'@5Hcpu@503cpuarm,cortex-a12P'@5Hcpu-opp-tableoperating-points-v2aHopp-126000000ls opp-216000000l s opp-312000000ls opp-408000000lQs opp-600000000l#Fs opp-696000000l)|s~opp-816000000l0,sB@opp-1008000000l<sopp-1200000000lGsopp-1416000000lTfrsOopp-1512000000lZJs opp-1608000000l_"spamba simple-busdma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkHdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkHRreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mH timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample)  @4reset disableddwmmc@ff0d0000rockchip,rk3288-dw-mshcр 5Eswbiuciuciu-driveciu-sample) ! @4reset disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample) "@4reset disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample) #@4resetokay@J\gudefault saradc@ff100000rockchip,saradc $5I[saradcapb_pclkW 4saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,udefault disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -udefault disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .udefault disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mudefault disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5Oudefault disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pudefault  disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qudefault! disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkudefault" disabledserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkudefault# disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkudefault$okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkudefault% disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkudefault& disabledthermal-zonesreserve_thermal'cpu_thermald'tripscpu_alert0ppassiveH(cpu_alert1$passiveH)cpu_crit_ criticalcooling-mapsmap0( map1) gpu_thermald'tripsgpu_alert0ppassiveH*gpu_crit_ criticalcooling-mapsmap0* tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 4tsadc-apbuinitdefaultsleep+$,.+8Ns disabledH'ethernet@ff290000rockchip,rk3288-gmac)emacirqeth_wake_irqu-85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 4stmmacethokay.inputudefault/0123rgmii 'B@ 40usb@ff500000 generic-ehciP 5usbhost5usbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otg&host6 usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg&otg.@O@@ 7 usb2-phyokayusb@ff5c0000 generic-ehci\ 5usbhostokayi2c@ff650000rockchip,rk3288-i2ce <i2c5Ludefault8okaypmic@1brockchip,rk808&9xin32krk808-clkout2udefault:;^<<<<<<======regulatorsDCDC_REG1!5G q_pwvdd_armH regulator-state-memDCDC_REG2!5G P_wvdd_gpuHkregulator-state-memB@DCDC_REG3!5wvcc_ddrregulator-state-memDCDC_REG4!5G2Z_2Zwvcc_ioH=regulator-state-mem2ZLDO_REG1!5G2Z_2Z wvccio_pmuregulator-state-mem2ZLDO_REG2!5G2Z_2Zwvcca_33regulator-state-memLDO_REG3!5GB@_B@wvdd_10regulator-state-memB@LDO_REG4!5Gw@_w@wvcc_wlregulator-state-memw@LDO_REG5!5Gw@_2Z wvccio_sdregulator-state-mem2ZLDO_REG6!5GB@_B@ wvdd10_lcdregulator-state-memB@LDO_REG7!5Gw@_w@wvcc_18regulator-state-memw@LDO_REG8!5Gw@_w@ wvcc18_lcdregulator-state-memw@SWITCH_REG1!5wvcc_sdregulator-state-memSWITCH_REG2!5wvcc_lanH3regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c5Nudefault> disabledpwm@ff680000rockchip,rk3288-pwmhudefault?5^pwm disabledpwm@ff680010rockchip,rk3288-pwmhudefault@5^pwm disabledpwm@ff680020rockchip,rk3288-pwmh udefaultA5^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0udefaultB5^pwm disabledbus_intmem@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsHpower-controller!rockchip,rk3288-power-controllerh HUpd_vio@9 5chgfdehilkj$CDEFGHIJKpd_hevc@11 5opLMpd_video@12 5Npd_gpu@13 5OPreboot-modesyscon-reboot-modeRB RBRB *RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvu-6Hjk$C#gׄeрxhрxhHsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwH-edp-phyrockchip,rk3288-dp-phy5h24mX disabledHeio-domains"rockchip,rk3288-io-voltage-domain disabledusbphyrockchip,rk3288-usb-phyokayudefaultQ c9usb-phy@320X 5]phyclkH7usb-phy@334X45^phyclkH5usb-phy@348XH5_phyclkH6watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdifr hclkmclk5TRtx 6udefaultSu- disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2sr 5RRtxrxi2s_hclki2s_clk5RudefaultT disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk 4crypto-rstokayiommu@ff900800rockchip,iommu@ eiep_mmu5 aclkiface disablediommu@ff914000rockchip,iommu @P eisp_mmu5 aclkiface disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkU ilm 4coreaxiahbvop@ff930000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopU def 4axiahbdclkVokayportH endpoint@0WHhendpoint@1XHfendpoint@2YH`endpoint@3ZHciommu@ff930300rockchip,iommu  evopb_mmu5 aclkifaceU okayHVvop@ff940000rockchip,rk3288-vop 5aclk_vopdclk_vophclk_vopU  4axiahbdclk[okayportH endpoint@0\Hiendpoint@1]Hgendpoint@2^Haendpoint@3_Hdiommu@ff940300rockchip,iommu  evopl_mmu5 aclkifaceU okayH[mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkU u- disabledportsportendpoint@0`HYendpoint@1aH^lvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdsulcdcbU u- disabledportsport@0endpoint@0cHZendpoint@1dH_dp@ff970000rockchip,rk3288-dp@ b5icdppclkedpo4dpu- disabledportsport@0endpoint@0fHXendpoint@1gH]hdmi@ff980000rockchip,rk3288-dw-hdmiru- g5hmniahbisfrcecU okayportsportendpoint@0hHWendpoint@1iH\iommu@ff9a0800rockchip,iommu evpu_mmu5 aclkiface disablediommu@ff9c0440rockchip,iommu @@@ o ehevc_mmu5 aclkiface disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ ejobmmugpu5jU okaykgpu-opp-tableoperating-points-v2Hjopp@100000000ls~opp@200000000l s~opp@300000000lsB@opp@400000000lׄsopp@500000000lesOopp@600000000l#Fsqos@ffaa0000syscon HOqos@ffaa0080syscon HPqos@ffad0000syscon HDqos@ffad0100syscon HEqos@ffad0180syscon HFqos@ffad0400syscon HGqos@ffad0480syscon HHqos@ffad0500syscon HCqos@ffad0800syscon HIqos@ffad0880syscon HJqos@ffad0900syscon HKqos@ffae0000syscon HNqos@ffaf0000syscon HLqos@ffaf0080syscon HMinterrupt-controller@ffc01000 arm,gic-400&@ @ `   Hefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrlu-gpio0@ff750000rockchip,gpio-banku Q5@7G&H9gpio1@ff780000rockchip,gpio-bankx R5A7G&gpio2@ff790000rockchip,gpio-banky S5B7G&gpio3@ff7a0000rockchip,gpio-bankz T5C7G&gpio4@ff7b0000rockchip,gpio-bank{ U5D7G&H4gpio5@ff7c0000rockchip,gpio-bank| V5E7G&gpio6@ff7d0000rockchip,gpio-bank} W5F7G&gpio7@ff7e0000rockchip,gpio-bank~ X5G7G&gpio8@ff7f0000rockchip,gpio-bank Y5H7G&hdmihdmi-cec-c0Slhdmi-cec-c7Slhdmi-ddc Sllpcfg-pull-upaHmpcfg-pull-downnHnpcfg-pull-none}Hlpcfg-pull-none-12ma} Hosleepglobal-pwroffSlH;ddrio-pwroffSlddr0-retentionSmddr1-retentionSmedpedp-hpdS ni2c0i2c0-xfer SllH8i2c1i2c1-xfer SllHi2c2i2c2-xfer S l lH>i2c3i2c3-xfer SllHi2c4i2c4-xfer SllH i2c5i2c5-xfer SllH!i2s0i2s0-bus`SllllllHTlcdclcdc-ctl@SllllHbsdmmcsdmmc-clkSlsdmmc-cmdSmsdmmc-cdSmsdmmc-bus1Smsdmmc-bus4@Smmmmsdio0sdio0-bus1Smsdio0-bus4@Smmmmsdio0-cmdSmsdio0-clkSlsdio0-cdSmsdio0-wpSmsdio0-pwrSmsdio0-bkpwrSmsdio0-intSmsdio1sdio1-bus1Smsdio1-bus4@Smmmmsdio1-cdSmsdio1-wpSmsdio1-bkpwrSmsdio1-intSmsdio1-cmdSmsdio1-clkSlsdio1-pwrS memmcemmc-clkSlH emmc-cmdSmHemmc-pwrS mHemmc-bus1Smemmc-bus4@Smmmmemmc-bus8SmmmmmmmmHspi0spi0-clkS mHspi0-cs0S mHspi0-txSmHspi0-rxSmHspi0-cs1Smspi1spi1-clkS mHspi1-cs0S mHspi1-rxSmHspi1-txSmHspi2spi2-cs1Smspi2-clkSmHspi2-cs0SmHspi2-rxSmHspi2-txS mHuart0uart0-xfer SmlH"uart0-ctsSmuart0-rtsSluart1uart1-xfer Sm lH#uart1-ctsS muart1-rtsS luart2uart2-xfer SmlH$uart3uart3-xfer SmlH%uart3-ctsS muart3-rtsS luart4uart4-xfer SmlH&uart4-ctsS muart4-rtsS ltsadcotp-gpioS lH+otp-outS lH,pwm0pwm0-pinSlH?pwm1pwm1-pinSlH@pwm2pwm2-pinSlHApwm3pwm3-pinSlHBgmacrgmii-pinsSlllloooolll oollH/rmii-pinsSllllllllllphy-intS mH2phy-pmebSmH1phy-rstSpH0spdifspdif-txS lHSpcfg-output-highHppcfg-output-lowpcfg-pull-none-drv-8mapcfg-pull-up-drv-8maapmicpmic-intSmH:usbphyhost-drvSlHQmemory@0memoryexternal-gmac-clock fixed-clocksY@ ext_gmacH.vsys-regulatorregulator-fixedwvcc_sysGLK@_LK@!5H< #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclockscpu0-supplyphandleoperating-pointsopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeeddisable-wpnon-removablepinctrl-namespinctrl-0#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsvbus_drv-gpios#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-low